Plotting ITIC Points

[dinos]

Hello,

I'm trying to find information on how voltage disturbance points "should" be plotted on the ITIC curve in terms of their magnitude and duration.

I've attached a disturbance waveform recorded on a 120V (nominal) circuit.
Where would you 'put the point' on the ITIC curve for this disturbance? Would you plot it as more than one point?

For what it's worth, the meter I used does provide an ITIC curve with this event plotted but I don't want to influence the discussion as yet by showing how they did it (I'm in the process of contacting the meter manufacturer but technical support is sometimes lacking).

Thanks in advance for any insight you can provide.

 

[gar]

091015-1328 EST

dinos:

What is an ITIC curve?

I noticed on your plot reference to RMS voltage on the lower graph. RMS does not mean anything without defining the averaging time and maybe the synchronization with the input.

Looking at the bottom plot it appears that the black or red dots coincide with zero crossings. The associated RMS values with each dot tend to make sense if the RMS measurement is based on integration over a 1/2 cycle period. But eyeballing the RMS values for each of the distorted 1/2 waves does not appear to agree with the RMS value at each of the red dots.

The 98.5 if it is for the last 1/2 cycle looks too high. If the values are for the preceding full cycle, quantized at half cycle points, then the values may correlate better.

So how do my guesses compare to what is an ITIC curve?

I suggest that the disturbance starts at the end of the first positive half sine wave. And ends slightly before the negative peak that precedes the good positive peak.

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[dinos]

091015-1328 EST
I noticed on your plot reference to RMS voltage on the lower graph. RMS does not mean anything without defining the averaging time and maybe the synchronization with the input.

Looking at the bottom plot it appears that the black or red dots coincide with zero crossings. The associated RMS values with each dot tend to make sense if the RMS measurement is based on integration over a 1/2 cycle period. But eyeballing the RMS values for each of the distorted 1/2 waves does not appear to agree with the RMS value at each of the red dots.

The 98.5 if it is for the last 1/2 cycle looks too high. If the values are for the preceeding full cycle, quantized at half cycle points, then the values may correlate better.

Thanks for picking up on information I had intended to include but forgot...

The black and red dots are plotted every 1/2 cycle, but they represent the full cycle rms of the waveform preceeding where they are plotted. There are actually 256 data points per cycle comprising the waveforn shown, and I threw them into excel and did my own rms calcs to verify. Taking that into view I think you'll see how the dots correlate with the waveform.

 

[dinos]

091015-1328 EST

What is an ITIC curve?

ITIC = Information Technology Industry Council.

The forerunner to the ITIC curve was the CBEMA curve.

 

[gar]

091015-1614 EST

dinos:

Do you have a description of how an ITIC curve is generated, what information is it supposed to provide, and how does your lower plot differ from an ITIC curve?

What is the reason to do a full cycle RMS calculation vs a half cycle? Half cycle would provide faster and maybe cleaner response.

.

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[dinos]

Do you have a description of how an ITIC curve is generated, what information is it supposed to provide

The curve and explanantory notes are here:

http://www.itic.org/clientuploads/Oct2000Curve.pdf

What is the reason to do a full cycle RMS calculation vs a half cycle?

That's how the meter records the transient.

 

[gar]

091015-1707 EST

dinos:

Your reference is very good and clear, but complex.

I would classify your waveform as a sag or interruption. The duration is less than 2 cycles and thus can drop to zero during this time and stay in the safe area. Therefore a running average, maybe quantized to 1/2 cycle, of a two cycle RMS measurement might provide the information you need.

I will think on it more. Dinner time.

.

 

[dinos]

Your reference is very good and clear, but complex.

Thankfully, I didn't have to write it

I would classify your waveform as a sag or interruption. The duration is less than 2 cycles and thus can drop to zero during this time and stay in the safe area.

I would also classify it as a sag. As for dropping to zero I think that can happen for up to 20ms or 1.2 cycles based on my read of the curve.

I attached my plot of how I think the waveform disturbance could be plotted. Since the ITIC curve shows distinct 90%, 80%, and 70% lines, I plotted the disturbance as 3 points, those being the approximate times I estimated the rms voltage was below those thresholds. Each of the plotted points as it turns out, are inside the curve.

 

[gar]

091016-1246 EST

dinos:

You have an interesting interpretation of the translation of your data to the ITIC boundary curves.

In retrospect the definitions may not be as clear as I thought.

3.5) Voltage Sags
Two different RMS voltage sags are described. Generally, these transients result from application of heavy loads, as well
as fault conditions, at various points in the AC distribution system. Sags to 80% of nominal (maximum deviation of 20%)
are assumed to have a typical duration of up to 10 seconds, and sags to 70% of nominal (maximum deviation of 30%) are
assumed to have a duration of up to 0.5 seconds.
3.6) Dropout
A voltage dropout includes both severe RMS voltage sags and complete interruptions of the applied voltage, followed by
immediate re-application of the nominal voltage. The interruption may last up to 20 milliseconds. This transient typically
results from the occurrence and subsequent clearing of faults in the AC distribution system.

I believe what the Voltage Tolerance Envelope says is that if a sag or dropout occurs for less than 20 milliseconds, 1.2 cycles, that no matter how you measure the voltage (peak, RMS, average) during that period it does not matter what the voltage is, it can be zero. Their discussion would seem to imply that on either side of the 20 millisecond problem that the voltage needs to be nominal based on section "3 Discussion" in the ITI Application Note.

I do not believe that RMS voltage is the really important consideration for sags or dropouts. Since this is directed at IT applications it is most likely related to DC capacitor input filter power supplies. These will be designed with a time constant that probably allows a 1 cycle loss of power input. This also means that near full voltage is needed at the end of the 1.2 cycle period. Basically a whole cycle could be lost, but then the following cycle needs to be nominal. Really would be not less than 90% od nominal. So you could lose one positive peak followed by a loss of the following negative peak or vice versa.

A capacitor input filter power supply essentially uses the peak of the input voltage to charge the capacitor. Current only flows for a short time.

Assume a bridge rectifier off of the line feeding a capacitor input filter. Apply a 120 V sine wave input. Capacitor voltage will be 169.7 V minus diode drop. I apply this 120 V RMS for a while, and then switch to 120 V DC (same RMS voltage). The capacitor voltage drops to 120 V minus diode drop. This does not fail the criteria using RMS as the means of measuring the input voltage. Yet from a functional point of view at the output of the DC supply there is failure.

How should "3.5 Voltage Sags" be interpreted? I think for your distorted waveform RMS is not the correct measurement. However, assume RMS is a valid measure, measurements are quantized to start on a zero crossing, the RMS value is calculated for a 2 cycle period (meaning the time period of averaging is 2 cycles --- 32 milliseconds), and a running measurement is made every 1/2 cycle, then any RMS value obtained below 70% of nominal is failure. This is a tough criteria and may not really address the problem. I believe your waveform would fail this test.

Now consider your data. To put points on the ITIC plot from your data I believe you have to set a starting time reference point that will correspond to the left coordinate of the ITIC curve. I would pick the first negative zero crossing on your original plot, This is above the 122.2 V dot. Your first RMS value from this reference is 59.4 V because you have whole cycle calculations of RMS. Thus, at 16.6 MS on the ITIC I would plot 59.4 V. Next I need an RMS value from the first negative zero crossing to 1.5 cycles later. This will not be as large as 91.3 V and occurs at 25 MS. I believe your waveform fails the ITIC lower limit.

When longer times for sags are considered I conclude that this means you drop from nominal to a fixed steady value for that long time, like 70%, and this can last for 0.5 seconds and then must return to nominal.

One item missing from the ITI definitions is the meaning of their usage of RMS and its integration time period.

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[dinos]

You have an interesting interpretation of the translation of your data to the ITIC boundary curves.

I hope I'm getting close...

Thank you for your continued interest...I will get to work on digesting what you came up with. In the meantime I think its time I brought out the ITIC plot which made me ask this question in the 1st place.

I have attached that ITIC plot straight from how it was generated by the meter software, except for a hand drawn note highlighting the specific disturbance we are looking at...so ignore the other dots you see as they are associated with completely different disturbances.

The crux of the matter as I see it is that the meter seems to have plotted the lowest full cycle rms recorded (59.4V or 49.5% of nominal) during the sag event...for the time the rms voltage was lower than 90% of nominal! This seems incongruous to me and I'm trying to find out why the meter is doing that, and, is it the 'right' (or at least generally accepted) way to do it?

 

[gar]

091016-1554 EST

dinos:

I can not read your last plot. Too small.

In the ITI Note, "3) Discussion" we have

--- All conditions are assumed to be mutually exclusive at any point in time, and with the
exception of steady-state tolerances, are assumed to commence from the nominal voltage. The timing between
transients is assumed to be such that the ITE returns to equilibrium (electrical, mechanical, and thermal) prior to
commencement of the next transient.

I read this to mean that the last time the waveform is of its nominal value and shape is the starting time of the transient event. This might be extended to mean these decisions are made at voltage zero crossings.

Using zero crossings as the transient start and end points, then in your first plot I define these as --- start the point above 122.2, end the point above 91.3. This is a total period of 3*8.333 MS = 25 MS.

Rereading "3.5 Voltage Sags" your waveform is not a normal sag, but rather a severe sag, and thus classified as a dropout. There is no clear definition what an RMS voltage is in this case. Clearly the problem is no definition of averaging time. As I said earlier it does not matter what happens on the down side within 20 MS.

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[gar]

091017-0636 EST

Considering that we are dealing with electronic systems with capacitor input filters is it likely that these are being designed with large enough capacitors to provide adequate output voltage to tolerate 84 V for 0.5 seconds? Or is the design criteria to operate continuously at 84 V input?

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[dinos]

I can not read your last plot. Too small.

Strange... the file format and size are similar to my other attachments.
It shows the disturbance we are looking at, plotted on the ITIC by the meter as one point at 59.4V (49.5% of nominal 120V) for a duration of 25ms.

 

[dinos]

Now consider your data. To put points on the ITIC plot from your data I believe you have to set a starting time reference point that will correspond to the left coordinate of the ITIC curve. I would pick the first negative zero crossing on your original plot, This is above the 122.2 V dot. Your first RMS value from this reference is 59.4 V because you have whole cycle calculations of RMS. Thus, at 16.6 MS on the ITIC I would plot 59.4 V. Next I need an RMS value from the first negative zero crossing to 1.5 cycles later. This will not be as large as 91.3 V and occurs at 25 MS. I believe your waveform fails the ITIC lower limit.

I like your way of thinking...
I put the waveform through my rms spreadsheet and at 1.5 cycles (25ms) from the first negative zero crossing on my original plot (above the 122.2 V dot) the rms value was 83.9V...just shy of 84V (70% of nominal 120V), so that would indeed fall just outside of the ITIC.

I've contacted the meter manufacturer and am waiting for their response as to why they plot the point as 49.5% of nominal at a time of 25ms.

 

[gar]

091019-1200 EST

dinos:

If I look at your waveform disturbance from the perspective of a full-wave rectifier, capacitor input filter, and 2% drop per half cycle as the design criteria under full load, then since only two half cycles are lost the maximum peak-to-peak ripple is about 6% instead of the normal 2%. Seems to me this is a more important criteria than the RMS voltage.

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[dinos]

If I look at your waveform disturbance from the perspective of a full-wave rectifier, capacitor input filter, and 2% drop per half cycle as the design criteria under full load, then since only two half cycles are lost the maximum peak-to-peak ripple is about 6% instead of the normal 2%. Seems to me this is a more important criteria than the RMS voltage.

I'm going to have to admit ignorance on this...haven't read much about the design aspects of ITE equipment. Hopefully someone else will chime in...

For what it's worth, the recorded waveform we've been looking at is on the output of a static-transfer-switch-fed-transformer and which typically occurs on source transfers under load. The nitty-gritty requirements of the downstream equipment in terms of power quality are unknown and we may not have to get that deep, so at present we are just checking to see whether or not the resultant waveform is within the ITIC from a general standpoint. I can see why the ITIC is meant to be a general guide though as the specific requirements for end-use equipment will 'invariably vary'. Now there's a good word combo

 

[gar]

091019-1414 EST

dinos:

If we assume most electronic equipment converts input AC to DC, then the response of the DC supply to changes of the input AC will be our concern.

Further assume the conversion from AC to DC is via a diode(s) charging a capacitor, then the concern is how this DC voltage varies for changes in the AC input.

http://en.wikipedia.org/wiki/Diode_bridge
http://en.wikipedia.org/wiki/Reservoir_capacitor
http://www.brianroth.com/library/national-ps-design.pdf

In a capacitor input filter power supply only near the peak of the AC waveform does current flow from the AC supply. The starting point of conduction of the rectifier has been referred to as the cut-in point and the end of conduction as the cut-out. During this time the capacitor is being charged from the AC. From cut-out to the next cut-in the capacitor follows the standard exponential discharge curve of an RC circuit. For low ripple the time constant of the RC circuit is made long compared to the time between input current pulses. For small changes in voltage on this exponential curve you can assume a straight line. This why I estimated from 2% to 6% for your one full cycle of interruption.

If you have access to Electronics by Millman and Seely, 1951, then on pages 388, 390, and 391 are some waveforms.

A quick search of the Internet did not provide a good discussing of the waveform vs RC time constant. The above Internet references are only a partial help.

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[gar]

091019-1930 EST

dinos:

Make a print of your first plot. Put a vertical line at the center of each half wave. On the center line of the third half wave after the left good positive half wave put a dot at +160 V. Draw a straight line from this point to the 169 V peak of the left good half wave.

The values at the other two intersection points are 166 and 163 V. In a full wave rectifier all of the negative pulses are flipped to the positive side. Actually the DC voltage will never drop to 160 because this pulse will start to charge the capacitor slightly before dropping to 160 V.

Assume this power supply has been designed to work continuously at 95 V steady state. This a DC out of 134 V. This one full cycle lost does not lower the DC output voltage below the designed minimum value of 134 V. In fact there is a lot of margin.

If the design criteria uses a much higher ripple percentage, then your 1 cycle problem could be troublesome. With out solving the exponential equation I would expect problems to occur at about 10% ripple.

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[dinos]

Assume this power supply has been designed to work continuously at 95 V steady state. This a DC out of 134 V. This one full cycle lost does not lower the DC output voltage below the designed minimum value of 134 V. In fact there is a lot of margin

I'm not sure I'm following you 100%.

I calculated the rms value over the 1.5 cycle period following the "122.2V point" as 83.9V, and extended that calculation out to a 2 cycle rms which came out to be 94.7V. Both of these are below the 95V steady state you mention so I'm guessing there could be a problem.

 

[gar]

091020-1055 EST

dinos:

Please call me by phone and I can more readily describe what I am thinking. My phone number is at the bottom of any page on my website.
www.beta-a2.com

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