Arc Flash Paper
- Thread starter mull982
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zog
Senior Member
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- Charlotte, NC
Dont think I have ever seen a paper written on the subject. I assume you are talking about the LV side of a MV/LV transformer vs the MV side. Typical for industrial power systems. You have much higher fault currents on the LV side, plus there really is no protection between the LV windings and main breaker so the values are very high, the MV fuse wont clear a fault on the LV side very fast so the IEEE 1584 2 second rule is often used. After the LV main breaker the value are smaller but still high due to the lack of INST trips on most main breakers (Coordination issues) and the 0.3-0.5 ST trip times coupled with those high fault currents. This can be easily be fixed by installing something like a QT system on the mains.
I will be presenting an arc flash mitigation seminar at the 10 largest conferences over the next year, hope to see you at one. Powertest, Doble, Finepoint, IEEE, EPRI, etc....
mayanees
Senior Member
- Location
- Westminster, MD
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- Electrical Engineer and Master Electrician
Paper on the case for MV Data Centers
Paper on the case for MV Data Centers
mull982,
You might be referring to the attached document.
Our VP had me run SKM to check his IEEE 1584 calculations for a comparison between similar 480 and 4160 Volt systems, and credited me as a co-author.
The reason why the MV systems have less Incident Energy (IE) is that the arcing fault current for the MV systems is very close to the short-circuit current so it lets the trip mechanism operate in it's fastest region. Low Voltage arcing faults, on the other hand, are one the order of 1/2 of the value of the short-circuit current, so there's a significant delay that allows for the buildup of IE, often to the 2 second default value.
John M
Paper on the case for MV Data Centers
mull982,
You might be referring to the attached document.
Our VP had me run SKM to check his IEEE 1584 calculations for a comparison between similar 480 and 4160 Volt systems, and credited me as a co-author.
The reason why the MV systems have less Incident Energy (IE) is that the arcing fault current for the MV systems is very close to the short-circuit current so it lets the trip mechanism operate in it's fastest region. Low Voltage arcing faults, on the other hand, are one the order of 1/2 of the value of the short-circuit current, so there's a significant delay that allows for the buildup of IE, often to the 2 second default value.
John M
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