I guess we're still talking about two different scenarios. You're talking about unbalanced loads on the neutral, but I'm talking about a single phase to ground fault on a solidly-grounded system. But the more I think of it the phase CT's will see that current anyway and trip the relay out. Any thoughts on that?
Also we're using microprocessor-based relays, so from what I gather you're saying as long as the CT rating is above the FLA of the transformers, I shouldn't be worried?
I1+I2+I3=IN. By definition you will see a phase overcurrent but not necessarily enough to trip.
If you have a phase to phase fault it will be worst case kVA x 1000 / (480 x 1.732) / %Z assuming infinite bus on primary and dead short at the terminals plus inductive backfeeding. For a phase to neutral fault it will be 58% of the phase-phase fault (277 vs 480). But ground faults occur across the grounded conductors which are generally higher impedance. Hence NEC mandates ground fault tripping because at higher currents you can’t realistically expect phase over current protection to consistently trip on ground faults.
So no, no reason to go bigger.
It’s preferable to exceed “FLA” moderately but don’t go crazy with it, do not double because some relays won’t adjust below a tap if 0.5 (2.5 A minimum trip). I have gotten burned by this issue more than once. It doesn’t hurt to be moderately under, say no more than 70%. CTs have ratios, not kVAs. The kVA is expressed by burden. With microprocessor relays burden is meaningless because it is so low. We aren’t powering coils for induction discs.
If you look in the relay manual and get deeply into the ADC side of things you will realize.a couple things. The relay is over sampling at 16-32x, and it has a peak current limit of around 10x the rates input or 5 A in North America. This is obviously woefully short of handling say a mild 10 kA fault on say a 100:5 CT with a maximum linear input of 1 kA. The CT starts to clip in contrast at 100 A (20 x 5 A) and fully saturates quite a bit higher but the relay gave out long before the C.T. did. But we can look at how much it is flat topped (crest factor) and then estimate currents much higher albeit with reduced accuracy. SEL has a couple white papers describing how this works. Suffice to say there is a lot of digital magic going on in the background that you just don’t have to worry about.
CT books just don’t do any justice to this because they were written when relays were all induction disc style. They didn’t have much dynamic range anyways, they are slow, and have large burdens.
Also I think you missed residual or digital phase C.T. ground fault vs true neutrals. You just add I1+I2+I3 as vectors to calculate IN. It sees the vector sum (geometric mean) of the errors in each.of the three phases. In a high resistance ground where 10 A is reasonable for the resistor and you set the trip typically at half that or 5 A, a few Amos of errors will nuisance trip so a neutral CT is required (with a 0.020 A output). But with solidly grounded systems with a tap of say 10-25% or thousands of amps in your case the error in the vector sum is probably less than the ADC conversion noise.
You will be using some very large bushing CTs with big windows, thin cores, and 1-3% accuracy. Should be fairly inexpensive. Check CT vendors or larger transformer shops to see what’s available. Ritz might be a good starting point.
