Inner Layer PCB Trace Clearances - Table2 BS60079-7: 2015

[RyanSS]

Hello All...

I plan on using an Isolated Opto Coupled Voltage Detector (HCPL-3700) to detect OV and UV levels for a 110V Monitoring. Few questions:

1. Table2 of BS60079-7:2015 does not mention clearances between PCB traces in inner layer (Or maybe I missed it). Can anyone help me with what should be the separation for a working voltage (WV) of 110Vrms +15%.
2. Is there a requirement for trace separation between adjacent layers ( vertically) for WV of 110Vrms
3. The isolated opto voltage detector (HCPL3700) requires external series resistors that are used to set the threshold levels. When the 110V is applied, most of the voltage is dropped across these resistors. In effect the voltage seen across the input of the opto coupler is about 7Vrms. In such a case:
a.) Does the Anode and Cathode (i.e., input) of the opto,, need to be treated as separate conductors and hence maintain separation per 110V rated voltage requirement
b.) Or does the input side of the opto need to be treated as the same "110V signal group" and only maintain separation to the isolated section?

Thanks

 

[tom baker]

This is a forum on the NEC, this question is way out of scope for what we normally answer. But I have been suprised on answers before